TDA5235
Appendix
Register Description
ꢀ
ꢁ
3//)5$&ꢁ&ꢁ
Z
Field
Bits
Type
Description
PLLFRAC1C1 7:0
w
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07H
PLL Fractional Division Ratio Register 2 Channel 1
A_PLLFRAC2C1
Offset
05CH
Reset Value
09H
PLL Fractional Division Ratio Register 2
Channel 1
ꢀ
ꢃ
ꢈ
ꢄ
ꢁ
3//)&20
3&ꢁ
8186('
3//)5$&ꢂ&ꢁ
ꢂ
Z
Z
Field
UNUSED
Bits
7:6
Type
Description
-
UNUSED
Reset: 0H
PLLFCOMPC1 5
w
w
Fractional Spurii Compensation enable for Channel 1
0B
1B
Disabled
Enabled
Reset: 0H
PLLFRAC2C1 4:0
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09H
Special Function Register Page Register
SFRPAGE
Offset
080H
Reset Value
00H
Special Function Register Page Register
Data Sheet
225
V1.0, 2010-02-19
INFINEON [ Infineon ]
