TDA5235
Appendix
Register Description
RSSI Peak Detector Bit Position Register
A_PKBITPOS
Offset
037H
Reset Value
00H
RSSI Peak Detector Bit Position Register
ꢀ
ꢁ
566,'/<
Z
Field
Bits
Type
Description
RSSIDLY
7:0
w
RSSI Detector Start-up Delay for RSSIPPL register
Min: 00h: 0 bit delay (Start with first bit after FSYNC)
Max: FFh: 255 bit delay
Note: Due to filtering and signal computation, the latency T1 and T2 have
to be added
Reset: 00H
Image Supression Fc Selection Register
A_ISUPFCSEL
Offset
038H
Reset Value
07H
Image Supression Fc Selection Register
ꢀ
ꢄ
ꢅ
ꢆ
ꢁ
8186('
5HV
)&6(/
ꢂ
Z
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
FCSEL
2:0
w
Image Supression Filter Corner Frequency Selection for FSK signal
path
000B 33 kHz
001B 46 kHz
010B 65 kHz
011B 93 kHz
100B 132 kHz
101B 190 kHz
110B 239 kHz
111B 282 kHz
Reset: 7H
Data Sheet
204
V1.0, 2010-02-19
INFINEON [ Infineon ]
