TDA5235
Appendix
Register Description
Field
Bits
Type
Description
UNUSED
7:4
-
UNUSED
Reset: 0H
AFCLIMIT
3:0
w
AFC Frequency Offset Saturation Limit ==> 1...15 x 21.4 kHz
Min: 1h = +/- Fsys / 2^(22-12) Hz
Max: Fh = +/- 15 * Fsys / 2^(22-12) Hz
Reg. value 0h = 0 Hz - no AFC correction
Reset: 2H
AFC/AGC Freeze Delay Register
A_AFCAGCD
Offset
02BH
Reset Value
00H
AFC/AGC Freeze Delay Register
ꢀ
ꢁ
$)&$*&'
Z
Field
Bits
Type
Description
AFCAGCD
7:0
w
AFC/AGC Freeze Delay Counter Division Ratio
The base period for the delay counter is the 8-16 samples/chip
(predecimation strobe) divided by 4
Reset: 00H
AFC Start/Freeze Configuration Register
A_AFCSFCFG
Offset
02CH
Reset Value
00H
AFC Start/Freeze Configuration Register
ꢀ
ꢃ
ꢈ
ꢄ
ꢆ
ꢇ
ꢁ
$)&%/$6 $)&5(6$
8186('
$)&)5((=(
$)&67$57
.
7&&
ꢂ
Z
Z
Z
Z
Field
Bits
Type
Description
UNUSED
7
-
UNUSED
Reset: 0H
Data Sheet
196
V1.0, 2010-02-19
INFINEON [ Infineon ]
