TDA5235
Appendix
Register Description
ꢀ
ꢁ
:8566,%/ꢁ
Z
Field
WURSSIBL1
Bits
Type
Description
7:0
w
Wake Up on RSSI Blocking Level LOW for Channel 1
Reset: FFH
RSSI Wake-Up Blocking Level High Channel 1 Register
A_WURSSIBH1
Offset
01DH
Reset Value
00H
RSSI Wake-Up Blocking Level High Channel
1 Register
ꢀ
ꢁ
:8566,%+ꢁ
Z
Field
Bits
Type
Description
WURSSIBH1 7:0
w
Wake Up on RSSI Blocking Level HIGH for Channel 1, when RSSI is
selected as WU criterion or FFB criterion.
In case of Signal Recognition as WU criterion or FFB criterion, the
register defines the minimum consecutive T/16 samples of the Signal
Recognition output to be at high level for a positive wake up event
generation or FFB generation
Reset: 00H
Signal Detector Saturation Threshold Register
A_SIGDETSAT
Offset
024H
Reset Value
10H
Signal Detector Saturation Threshold
Register
ꢀ
ꢁ
6,*'(76$7
Z
Data Sheet
192
V1.0, 2010-02-19
INFINEON [ Infineon ]
