TDA5235
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
B_TVWIN
Register Long Name
Offset Address Page Number
Timing Violation Window Register
Slicer Configuration Register
14BH
14CH
14DH
14EH
14FH
150H
151H
152H
153H
154H
155H
156H
157H
158H
159H
B_SLCCFG
B_TSIMODE
B_TSILENA
B_TSILENB
B_TSIGAP
TSI Detection Mode Register
TSI Length Register A
TSI Length Register B
TSI Gap Length Register
B_TSIPTA0
TSI Pattern Data Reference A Register 0
TSI Pattern Data Reference A Register 1
TSI Pattern Data Reference B Register 0
TSI Pattern Data Reference B Register 1
End Of Message Control Register
EOM Data Length Limit Register
EOM Data Length Limit Parallel Mode Register
Channel Configuration Register
PLL MMD Integer Value Register Channel 1
B_TSIPTA1
B_TSIPTB0
B_TSIPTB1
B_EOMC
B_EOMDLEN
B_EOMDLENP
B_CHCFG
B_PLLINTC1
B_PLLFRAC0C1
B_PLLFRAC1C1
B_PLLFRAC2C1
PLL Fractional Division Ratio Register 0 Channel 1 15AH
PLL Fractional Division Ratio Register 1 Channel 1 15BH
PLL Fractional Division Ratio Register 2 Channel 1 15CH
Table 2
Register Overview and Reset Value
Register Short Name
Register Long Name
Offset Address Reset Value
Appendix - Registers Chapter, Register Description
A_MID0
A_MID1
A_MID2
A_MID3
A_MID4
A_MID5
A_MID6
A_MID7
A_MID8
A_MID9
A_MID10
A_MID11
A_MID12
A_MID13
A_MID14
A_MID15
Message ID Register 0
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
Message ID Register 15
000H
001H
002H
003H
004H
005H
006H
007H
008H
009H
00AH
00BH
00CH
00DH
00EH
00FH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Data Sheet
172
V1.0, 2010-02-19
INFINEON [ Infineon ]
