TDA5235
Appendix
Register Overview
Table 1
Register Overview (cont’d)
Register Short Name
RSSISLOPE
Register Long Name
Offset Address Page Number
RSSI Slope Register
091H
092H
237
237
CDRDRTHRP
CDR Data Rate Acceptance Positive Threshold
Register
CDRDRTHRN
CDR Data Rate Acceptance Negative Threshold 093H
Register
238
IM0
Interrupt Mask Register 0
094H
096H
097H
098H
099H
09AH
09BH
09CH
09DH
09EH
09FH
0A4H
0A5H
0A6H
0A7H
0A8H
0AAH
238
239
240
240
241
241
242
242
243
243
244
244
245
246
247
248
249
SPMAP
Self Polling Mode Active Periods Register
Self Polling Mode Idle Periods Register
Self Polling Mode Control Register
SPMIP
SPMC
SPMRT
Self Polling Mode Reference Timer Register
Self Polling Mode Off Time Register 0
Self Polling Mode Off Time Register 1
Self Polling Mode On Time Config A Register 0
Self Polling Mode On Time Config A Register 1
Self Polling Mode On Time Config B Register 0
Self Polling Mode On Time Config B Register 1
External Processing Command Register
Chip Mode Control Register 1
SPMOFFT0
SPMOFFT1
SPMONTA0
SPMONTA1
SPMONTB0
SPMONTB1
EXTPCMD
CMC1
CMC0
Chip Mode Control Register 0
RSSIPWU
IS0
Wakeup Peak Detector Readout Register
Interrupt Status Register 0
RFPLLACC
RF PLL Actual Channel and Configuration
Register
RSSIPRX
RSSIPPL
PLDLEN
ADCRESH
ADCRESL
VACRES
AFCOFFSET
AGCGAINR
SPIAT
RSSI Peak Detector Readout Register
RSSI Payload Peak Detector Readout Register
Payload Data Length Register
ADC Result High Byte Register
ADC Result Low Byte Register
VCO Autocalibration Result Readout Register
AFC Offset Read Register
0ABH
0ACH
0ADH
0AEH
0AFH
0B0H
0B1H
0B2H
0B3H
0B4H
0B5H
0B6H
0B7H
0B8H
0B9H
0BAH
250
250
251
251
252
252
252
253
253
254
254
255
255
255
256
256
AGC Gain Readout Register
SPI Address Tracer Register
SPI Data Tracer Register
SPIDT
SPICHKSUM
SN0
SPI Checksum Register
Serial Number Register 0
SN1
Serial Number Register 1
SN2
Serial Number Register 2
SN3
Serial Number Register 3
RSSIRX
RSSI Readout Register
Data Sheet
169
V1.0, 2010-02-19
INFINEON [ Infineon ]
