TDA 5210
Functional Description
gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset
produced by the demodulator in case of large frequency offsets of the IF signal.
The resulting frequency characteristic and details on the principle of operation
of the switch are described in Section 4.6.
Table 3-4 MSEL Pin Operating States
MSEL
Modulation Format
Open
ASK
FSK
Shorted to ground
The demodulator circuit is switched off in case of reception of ASK signals.
3.4.7 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100kΩ on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
3.4.8 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of up to 100kBaud. The maximum achievable
data rate also depends on the IF Filter bandwidth and the local oscillator toler-
ance values. Both inputs are accessible. The output delivers a digital data sig-
nal (CMOS-like levels) for sbsequent circuits. The self-adjusting threshold on
pin 20 its generated by RC-term or peak detector depending on the baseband
coding scheme. The data slicer threshold generation alternatives are described
in more detail in Section 4.5.
3.4.9 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. An external RC network is necessary. The input
is connected to the output of the RSSI-output of the Limiter, the output is con-
nected to the PDO pin (Pin 26 ). This output can be used as an indicator for the
received signal strength to use in wake-up circuits and as a reference for the
data slicer in ASK mode. The maximum output current is typically 950µA, the
discharge current is lower than 2µA. Note that the RSSI level is also output in
case of FSK mode.
Wireless Components
3 - 12
Specification, May 2001
INFINEON [ Infineon ]
