TDA 5210
Functional Description
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen
along with the appropriate threshold voltage according to the intended operat-
ing case and interference scenario to be expected during operation. The opti-
mum choice of AGC time constant and the threshold voltage is described in
Section 4.1.
3.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the
range of 400-440MHz/810-870MHz to the intermediate frequency (IF) at
10.7MHz with a voltage gain of approximately 21dB by utilising either high- or
low-side injection of the local oscillator signal. In case the mixer is interfaced
only single-ended, the unused mixer input has to be tied to ground via a capac-
itor. The mixer is followed by a low pass filter with a corner frequency of 20MHz
in order to suppress RF signals to appear at the IF output (IFO pin). The IF out-
put is internally consisting of an emitter follower that has a source impedance
of approximately 330 Ω to facilitate interfacing the pin directly to a standard
10.7MHz ceramic filter without additional matching circuitry.
3.4.3 PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous
divider chain, a phase detector with charge pump and a loop filter and is fully
implemented on-chip. The VCO is including on-chip spiral inductors and varac-
tor diodes. It’s nominal centre frequency is 840MHz, the operating range guar-
anteed over the temperature range specified is 820 to 860MHz. Depending on
whether high- or low-side injection of the local oscillator is used the receive fre-
quency ranges are 810 to 840 and 840 to 870MHz or 400 to 420 and 420 to
440MHz (see also Section 4.4). No additional external components are neces-
sary.
The oscillator signal is fed both to the synthesiser divider chain and to the down-
converting mixer. In case of operation in the 400 to 440 MHz range, the signal
is divided by two before it is fed to the mixer. This is controlled by the selection
pin FSEL (Pin 11) as described in the following table. The overall division ratio
of the divider chain can be selected to be either 128 or 64, depending on the
frequency of the reference oscillator quartz (see below and Section 4.4). The
loop filter is also realised fully on-chip.
Table 3-2 FSEL Pin Operating States
FSEL
RF Frequency
400-440 MHz
810-870 MHz
Open
Shorted to ground
Wireless Components
3 - 10
Specification, May 2001
INFINEON [ Infineon ]
