TC1796
Functional Description
3.7
DMA Controller and Memory Checker
The Direct Memory Access (DMA) Controller of the TC1796 transfers data from data
source locations to data destination locations without intervention of the CPU or other
on-chip devices. One data move operation is controlled by one DMA channel. Sixteen
DMA channels are provided in two independent DMA Sub-Blocks with eight DMA
channels each. The Bus Switch provides the connection of two DMA Sub-Blocks to the
two FPI Bus interfaces and an MLI bus interface. In the TC1796, the FPI Bus interfaces
are connected to System Peripheral Bus and the Remote Peripheral Bus. The third
specific bus interface provides a connection to Micro Link Interface modules (two MLI
modules in the TC1796) and other DMA-related devices (Memory Checker module in the
TC1796). Figure 6 shows the implementation details and interconnections of the DMA
module.
fDMA
DMA Controller
DMA Sub-Block 0
Clock
Control
System
Peripheral
Bus
DMA
Channels
00-07
Request
Selection/
Arbitration
Transaction
Control Unitl
DMA
Requests of
On-chip
Periph.
Remote
Peripheral
Bus
CH0n_OUT
Bus
Switch
Units
DMA Sub-Block 1
DMA
Channels
10-17
MLI0
MLI1
Request
Selection/
Arbitration
Address
Decoder
Transaction
Control Unit
Memory
Checker
CH1n_OUT
Arbiter/
Switch
Control
Interrupt
Request
Nodes
SR[15:0]
DMA Interrupt Control
MCB05680
Figure 6
DMA Controller Block Diagram
Data Sheet
44
V1.0, 2008-04
INFINEON [ Infineon ]
