TC1796
Functional Description
3.9
Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1)
Figure 8 shows a global view of the functional blocks and interfaces of the two
Asynchronous/Synchronous Serial Interfaces ASC0 and ASC1.
fASC
Clock
Control
P5.0 /
RXD0A
A2
A2
RXD_I0
RXD_I1
RXD_O
TXD_O
P5.1 /
TXD0A
Address
Decoder
ASC0
Module
(Kernel)
P6.8 /
RXD0B
A2
A2
EIR
TBIR
TIR
P6.9 /
TXD0B
Interrupt
Control
RIR
Port 5
&
Port 6
Control
ASC0_RDR
ASC0_TDR
To
DMA
P5.2 /
RXD1A
A2
A2
RXD_I0
RXD_I1
RXD_O
TXD_O
P5.3 /
TXD1A
ASC1
Module
(Kernel)
P6.10 /
RXD1B
A2
A2
EIR
TBIR
TIR
P6.11 /
TXD1B
Interrupt
Control
RIR
ASC1_RDR
ASC1_TDR
To
DMA
MCB05773
Figure 8
Block Diagram of the ASC Interfaces
The Asynchronous/Synchronous Serial Interfaces provide serial communication
between the TC1796 and other microcontrollers, microprocessors, or external
peripherals.
The ASC supports full-duplex asynchronous communication and half-duplex
synchronous communication. In Synchronous Mode, data is transmitted or received
synchronous to a shift clock which is generated by the ASC internally. In Asynchronous
Data Sheet
48
V1.0, 2008-04
INFINEON [ Infineon ]
