TC1796
Functional Description
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Data buffering supported
– Code prefetch buffer
– Read/write buffer
External bus arbitration control capability for the EBU bus
Automatic self-configuration on boot from external memory
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3.6
Peripheral Control Processor
The Peripheral Control Processor (PCP2) in the TC1796 performs tasks that would
normally be performed by the combination of a DMA controller and its supporting CPU
interrupt service routines in a traditional computer system. It could easily be considered
as the host processor’s first line of defence as an interrupt-handling engine. The PCP2
can off-load the CPU from having to service time-critical interrupts. This provides many
benefits, including:
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Avoiding large interrupt-driven task context-switching latencies in the host processor
Reducing the cost of interrupts in terms of processor register and memory overhead
Improving the responsiveness of interrupt service routines to data-capture and data-
transfer operations
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Easing the implementation of multitasking operating systems.
The PCP2 has an architecture that efficiently supports DMA-type transactions to and
from arbitrary devices and memory addresses within the TC1796 and also has
reasonable stand-alone computational capabilities.
The PCP2 in the TC1796 contains an improved version of the TC1775’s PCP with the
following enhancements:
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Optimized context switching
Support for nested interrupts
Enhanced instruction set
Enhanced instruction execution speed
Enhanced interrupt queueing
The PCP2 is made up of several modular blocks as follows (see Figure 5):
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PCP2 Processor Core
Code Memory (CMEM)
Parameter Memory (PRAM)
PCP2 Interrupt Control Unit (PICU)
PCP2 Service Request Nodes (PSRN)
System bus interface to the Flexible Peripheral Interface (FPI Bus)
Data Sheet
42
V1.0, 2008-04
INFINEON [ Infineon ]
