TC1796
Functional Description
3.3
Architectural Address Map
Table 5 shows the overall architectural address map as defined for the TriCore and
implemented in TC1796.
Table 5
TC1796 Architectural Address Map
Seg- Contents
Size
Description
ment
0-7
8
Global
8 × 256
Reserved (MMU space), cached
Mbyte
Global
Memory
256 Mbyte EBU (246 Mbyte), PMU with PFLASH, DFLASH,
BROM, memory reserved for Emulation, cached
9
Global
Memory
256 Mbyte FPI space; cached
10
Global
Memory
256 Mbyte EBU (246 Mbyte), PMU with PFLASH, DFLASH,
BROM, memory reserved for Emulation, non-
cached
11
12
13
Global
256 Mbyte FPI space; non-cached
Memory
Local LMB
Memory
DMI
PMI
EXTPER
EXTEMU
256 Mbyte DMU, bottom 4 Mbyte visible from FPI Bus in
segment 14, cached
64 Mbyte
64 Mbyte
96 Mbyte
16 Mbyte
Local Data Memory RAM, non-cached
Local Code Memory RAM, non-cached
External Peripheral Space, non-cached
External Emulator Range, non-cached
Boot ROM space, BROM mirror; non-cached
BOOTROM 16 Mbyte
14
15
EXTPER
128 Mbyte External Peripheral Space non-speculative, no
execution, non-cached
CPU[0 ..15] 16 × 8
image region Mbyte
Non-speculative, no execution, non-cached
LMBPER
CSFRs
INTPER
256
Mbyte
CSFRs of CPUs[0 ..15];
LMB & Internal Peripheral Space; non-speculative,
no execution, non-cached
Data Sheet
39
V1.0, 2008-04
INFINEON [ Infineon ]
