TC39x BC/BD-Step
Electrical SpecificationInter-IC (I2C) Interface Timing
3.27
Inter-IC (I2C) Interface Timing
All I2C timing parameter are SR for Master Mode and CC for Slave Mode.
Table 3-63 I2C Standard Mode Timing
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Fall time of both SDA and SCL t1
-
-
300
ns
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Capacitive load for each bus line Cb SR
-
-
-
400
-
pF
µs
Bus free time between a STOP t10
4.7
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
and ATART condition
Rise time of both SDA and SCL t2
-
-
-
-
-
-
-
-
-
1000
ns
µs
ns
µs
µs
µs
µs
µs
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data hold time
t3
t4
t5
t6
t7
t8
0
-
-
-
-
-
-
-
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data set-up time
250
4.7
4
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Low period of SCL clock
High period of SCL clock
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Hold time for the (repeated)
START condition
4
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Set-up time for (repeated)
START condition
4.7
4
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Set-up time for STOP condition t9
Measured with a pull-
up resistor of 4.7 kohms
at each of the SCL and
SDA line
Data Sheet
497
V 1.2, 2021-03
OPEN MARKET VERSION
INFINEON [ Infineon ]
