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SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

SAK-TC399XP-256F300S BC图片预览
型号: SAK-TC399XP-256F300S BC
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内容描述: [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
分类和应用:
文件页数/大小: 548 页 / 21256 K
品牌: INFINEON [ Infineon ]
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TC39x BC/BD-Step  
Electrical SpecificationE-Ray Parameters  
3.25  
E-Ray Parameters  
The timings of this section are valid for the strong driver and sharp edge settings of the output drivers with CL =  
25 pF.  
Table 3-58 Transmit Parameters  
Parameter  
Symbol  
Values  
Typ.  
Unit  
Note / Test Condition  
Min.  
Max.  
Rise time of TxEN  
Fall time of TxEN  
tdCCTxENRise2  
5 CC  
-
-
-
-
-
9
ns  
ns  
ns  
ns  
CL=25pF  
tdCCTxENFall25  
CC  
-
-
-
9
CL=25pF  
Sum of rise and fall time  
tdCCTxRise25+d  
CCTxFall25 CC  
9
20% - 80% ; CL=25pF  
Sum of delay between TP1_FF tdCCTxEN01  
25  
and TP1_CC and delays  
derived from TP1_FFi, rising  
edge of TxEN  
CC  
Sum of delay between TP1_FF tdCCTxEN10  
-
-
25  
ns  
and TP1_CC and delays  
derived from TP1_FFi, falling  
edge of TxEN  
CC  
Asymmetry of sending  
t
tx_asym CC -2.45  
-
-
2.45  
25  
ns  
ns  
CL=25pF  
Sum of delay between TP1_FF tdCCTxD01 CC -  
and TP1_CC and delays  
derived from TP1_FFi, rising  
edge of TxD  
Sum of delay between TP1_FF tdCCTxD10 CC -  
and TP1_CC and delays  
derived from TP1_FFi, falling  
edge of TxD  
-
-
25  
9
ns  
ns  
TxD signal sum of rise and fall  
time at TP1_BD  
t
txd_sum CC  
-
Table 3-59 Receive Parameters  
Parameter  
Symbol  
Values  
Unit  
Note / Test Condition  
Min.  
Typ.  
Max.  
Acceptance of asymmetry at  
receiving part  
tdCCTxAsymAcc -30.5  
ept25 SR  
-
43.0  
ns  
ns  
%
%
CL=25pF  
CL=15pF  
Acceptance of asymmetry at  
receiving part  
tdCCTxAsymAcc -31.5  
ept15 SR  
-
-
-
44.0  
70  
Threshold for detecting logical TuCCLogic1  
high SR  
Threshold for detecting logical TuCCLogic0  
35  
30  
65  
low  
SR  
Data Sheet  
493  
V 1.2, 2021-03  
OPEN MARKET VERSION  
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