欢迎访问ic37.com |
会员登录 免费注册
发布采购

SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

SAK-TC399XP-256F300S BC图片预览
型号: SAK-TC399XP-256F300S BC
PDF下载: 下载PDF文件 查看货源
内容描述: [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
分类和应用:
文件页数/大小: 548 页 / 21256 K
品牌: INFINEON [ Infineon ]
 浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第459页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第460页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第461页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第462页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第464页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第465页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第466页浏览型号SAK-TC399XP-256F300S BC的Datasheet PDF文件第467页  
TC39x BC/BD-Step  
Electrical SpecificationReset Timing  
Table 3-30 Reset (cont’d)  
Parameter  
Symbol  
Values  
Typ.  
Unit  
Note / Test Condition  
Min.  
Max.  
HWCFG pins setup time to  
ESR0 rising edge  
t
HDS CC  
0
-
-
-
-
-
-
-
-
ns  
s
Ports inactive after ESR0 reset tPI CC  
active  
8000/fBAC  
18000/fBA  
KT  
CKT  
Ports inactive after PORST  
reset active  
t
t
t
t
PIP CC  
POH SR  
POS SR  
BWP CC  
-
150  
ns  
ns  
ns  
ms  
ms  
Hold time from PORST rising  
edge  
150  
-
Setup time to PORST rising  
edge  
0
-
-
Warm PORST reset boot time  
1.5  
6
without RAM  
initalization  
LBIST execution time extending tLBIST CC  
-
LBIST Configuration A;  
the boot time  
1.2V ≤ VDD  
SCR reset boot time  
t
SCR CC  
-
-
-
-
5
µs  
µs  
µs  
User Mode 0  
User Mode 1  
-
16  
-
13.3  
WDT double bit ECC,  
soft reset  
Minimum external supplies hold tSUPHOLD CC -  
-
250  
µs  
external supplies are  
time after warm reset assertion  
VEVRSB, VEXT, VFLEX  
,
VEBU, VDDM, VDDP3 and  
VDD  
1) RAM initialization add 500µs in addition.  
2) Cold PORST reset is driven by uC and maintained in an extended voltage range between VDDPPA limit and absolute  
maximum rating voltage limits.  
3) The reset release on supply ramp-up or supply restoration is delayed by a voltage hysteresis of 1.5% (default value) above  
the undervoltage reset limit implemented on VEXT, VDDP3 and VDD rails. This mechanism helps to avoid multiple consecutive  
cold PORST events during slow supply ramp-ups owing to voltage drop/current jumps when reset is released.  
Data Sheet  
463  
V 1.2, 2021-03  
OPEN MARKET VERSION  
 复制成功!