C167CR
C167SR
The C167CR also provides an excellent mechanism to identify and to process
exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar to a
standard interrupt service (branching to a dedicated vector table location). The
occurrence of a hardware trap is additionally signified by an individual bit in the trap flag
register (TFR). Except when another higher prioritized trap service is in progress, a
hardware trap will interrupt any actual program execution. In turn, hardware trap services
can normally not be interrupted by standard or PEC interrupts.
Table 4 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 4
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
–
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
RESET
RESET
RESET
00’0000H
00’0000H
00’0000H
00H
00H
00H
III
III
III
Class A Hardware Traps:
– Non-Maskable Interrupt NMI
NMITRAP 00’0008H
STOTRAP 00’0010H
STUTRAP 00’0018H
02H
04H
06H
II
II
II
– Stack Overflow
– Stack Underflow
STKOF
STKUF
Class B Hardware Traps:
– Undefined Opcode
– Protected Instruction
Fault
UNDOPC BTRAP
PRTFLT BTRAP
00’0028H
00’0028H
0AH
0AH
I
I
– Illegal Word Operand
Access
– Illegal Instruction
Access
– Illegal External Bus
Access
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
00’0028H
00’0028H
00’0028H
0AH
0AH
0AH
I
I
I
Reserved
–
–
–
–
[2CH –
3CH]
[0BH –
0FH]
–
Software Traps
– TRAP Instruction
Any
Any
Current
CPU
Priority
[00’0000H – [00H –
00’01FCH] 7FH]
in steps
of 4H
Data Sheet
21
V3.2, 2001-07
INFINEON [ Infineon ]
