C167CR
AC Characteristics
Definition of Internal Timing
The internal operation of the C167CR is controlled by the internal CPU clock fCPU. Both edges of the
CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time between
two consecutive edges of the CPU clock, called “TCL” (see figure below).
Figure 11
Generation Mechanisms for the CPU Clock
The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their
variation (and also the derived external timing) depends on the used mechanism to generate fCPU
.
This influence must be regarded when calculating the timings for the C167CR.
Direct Drive
When pin P0.15 (P0H.7) is low (‘0’) during reset the on-chip phase locked loop is disabled and the
CPU clock is directly driven from the oscillator with the input clock signal.
The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the
duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL
.
The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL
that is possible under the respective circumstances. This minimum value can be calculated via the
following formula:
TCL
= 1/fXTAL × DC
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the
duration of 2TCL is always 1/fXTAL. The minimum value TCL therefore has to be used only once
min
min
min
for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of
TCLs (2,4,...) may use the formula 2TCL = 1/fXTAL
.
Note: The address float timings in Multiplexed bus mode (t and t ) use the maximum duration of
11
45
TCL (TCL
= 1/fXTAL × DC
) instead of TCL
.
min
max
max
Semiconductor Group
44
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