C167CR
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
RD to valid data in
(with RW-delay)
t14 SR
t15 SR
t16 SR
t17 SR
t18 SR
t19 SR
–
–
–
–
0
–
30 + tC
–
–
–
–
0
–
2TCL – 20
+ tC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD to valid data in
(no RW-delay)
55 + tC
3TCL – 20
+ tC
ALE low to valid data in
55
+ tA + tC
3TCL – 20
+ tA + tC
Address to valid data in
70
+ 2tA + tC
4TCL – 30
+ 2tA + tC
Data hold after RD
rising edge
–
–
Data float after RD
Data valid to WR
Data hold after WR
35 + tF
2TCL – 15
+ tF
t22 SR 25 + tC
t23 CC 35 + tF
–
2TCL – 25
+ tC
–
–
2TCL – 15
+ tF
–
ALE rising edge after RD, t25 CC 35 + tF
WR
–
2TCL – 15
+ tF
–
Address hold after RD,
WR
t27 CC 35 + tF
t38 CC – 5 – tA
–
2TCL – 15
+ tF
–
ALE falling edge to CS
CS low to Valid Data In
10 – tA
– 5 – tA
10 – tA
ns
ns
t39 SR
–
55
–
3TCL – 20
+ tC + 2tA
+ tC + 2tA
CS hold after RD, WR
t40 CC 60 + tF
t42 CC 20 + tA
t43 CC – 5 + tA
–
3TCL – 15
+ tF
–
ns
ns
ns
ns
ns
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
–
TCL – 5
+ tA
–
ALE fall. edge to RdCS,
WrCS (no RW delay)
–
– 5
+ tA
–
Address float after RdCS, t44 CC
WrCS (with RW delay)
–
–
–
0
–
–
–
0
Address float after RdCS, t45 CC
WrCS (no RW delay)
25
TCL
RdCS to Valid Data In
(with RW delay)
t46 SR
25 + tC
2TCL – 25
+ tC
Semiconductor Group
48
INFINEON [ Infineon ]
