PEB 2091
PEF 2091
Functional Description
The dynamic characteristics of this clock are described in "LT Modes", page 281.
Clock CLS
This clock is not defined in this mode.
3.7.2
NT and TE Mode
U
U
XIN XOUT
XIN XOUT
CLS=7680 kHz
FSC=8 kHz
DCL=512 kHz
CLS=7680 kHz
FSC=8 kHz
DCL=1536 kHz
Interface
Interface
NT
TE
Synchr.
(Downstream)
Synchr.
(Downstream)
Figure 33
Clock in NT Mode
Figure 33
Clocks in TE Mode
In NT and TE modes the IEC-Q recovers the timing directly from the U-interface.
Synchronization to the U-interface is achieved by including correction steps in the divider
of the 15.36-MHz base clock. Thus the issued IOM®-2 clock signals are synchronous to
the PTT-master clock on LT side.
XIN/XOUT
A free running crystal or other clock source should provide a 15.36-MHz base clock (see
also “External Circuitry” on page 249 for more informations about crystal properties).
CLS Clock
In these modes the IEC-Q issues a 7.68-MHz clock signal. This clock signal is
synchronous to the received U-interface signal. In order to achieve synchronism the free
running 15.36-MHz master clock is not permanently divided by 2. Adjustment steps are
included by division with 1 or 3. It is not available in power down.
Semiconductor Group
85
Data Sheet 01.99
INFINEON [ Infineon ]
