PEB 2091
PEF 2091
Operational Description
Alerted by the MDR interrupt, the microprocessor reads the Monitor Receive (MOR)
register. When it is ready to accept data (e.g. based on the value in MOR, which in a
point-to-multipoint application might be the address of the destination device), it sets the
MR control bit MRC to "1" to enable the receiver to store succeeding Monitor Channel
bytes and acknowledge them according to the Monitor Channel protocol. In addition, it
enables other Monitor Channel interrupts by setting Monitor receive Interrupt Enable
(MRE) to "1".
As a result, the first Monitor byte is acknowledged by the receiving device setting the MR
bit to "0". This causes a Monitor Data Acknowledge (MDA) interrupt status at the
transmitter.
A new Monitor data byte can now be written by the microprocessor in MOX. The MX bit
is still in the active ("0") state. The transmitter indicates a new byte in the Monitor
Channel by returning the MX bit active after sending it once in the inactive state. As a
result, the receiver stores the Monitor byte in MOR and generates a new MDR interrupt
status. When the microprocessor has read the MOR register, the receiver acknowledges
the data by returning the MR bit active after sending it once in the inactive state. This in
turn causes the transmitter to generate an MDA interrupt status.
This "MDA interrupt – write data – MDR interrupt – read data – MDA interrupt"
handshake is repeated as long as the transmitter has data to send. Note that the Monitor
Channel protocol imposes no maximum reaction times to the microprocessor.
When the last byte has been acknowledged by the receiver (MDA interrupt status), the
microprocessor sets the Monitor Transmit Control bit (MXC) to "0". This enforces an
inactive ("1") state in the MX bit. Two frames of MX inactive signifies the end of a
message. Thus, a Monitor Channel End of Reception (MER) interrupt status is
generated by the receiver when the MX bit is received in the inactive state in two
consecutive frames. As a result, the microprocessor sets the MR control bit MRC to "0",
which in turn enforces an inactive state in the MR bit. This marks the end of the
transmission, making the Monitor Channel Active (MAC) bit return to "0".
During a transmission process, it is possible for the receiver to ask for a transmission to
be aborted by sending an inactive MR bit value in two consecutive frames. This is
effected by the microprocessor writing the MR control bit MRC to "0". An aborted
transmission is indicated by a Monitor Channel Data Abort (MAB) interrupt status at the
transmitter.
In TE mode, the ADF2:TE1 bit is used to direct the Monitor access either to
IOM®-2-channel 0 (ADF2:TE1 = "0", default) or to IOM®-2-channel 1 of the
IOM®-2-Terminal structure. This allows to program terminal devices such as the
ARCOFI® via the processor interface of the IEC-Q. If the ADF2:TE1 bit is "1", the Monitor
Channel on IOM®-2-channel 0 is passed transparently from the IOM®-2 interface to the
transceiver core.
Semiconductor Group
105
Data Sheet 01.99
INFINEON [ Infineon ]
