Functional Description
Protection Circuit for Unsymmetrical Receivers (PEB 2085)
For unsymmetrical S0-receivers (PEB 2085) a 2.5 V reference voltage is supplied at pin SR1
(output). The input signal at pin SR2 is referred to the level at pin SR1. In order to stabilize the
reference voltage, a 10 nF capacitor is used. Resistors between pin SR 1 and the transformer
should be avoided. Sometimes, however, a small resistor is required to improve the
Longitudinal Conversion Loss (LCL) performance; absolute maximum is 200 Ω.
At pin SR2 a low-pass filter of 1st or 2nd order may be provided to reject high frequency noise.
The overall impedace, however, should not exceed 10 kΩ to avoid input signal reduction due
to voltage division in conjunction with the internal impedance. In case no low-pass filter is
required the resistor may be omitted.
< 10 kΩ
SR2
47 pF
GND
1.8 V
VDD
S0 Bus
SR1
10 nF
2.2 kΩ
1.5 nF
ITS05642
Figure 48
External Circuitry for Unsymmetrical Receivers (PEB 2086)
The recommended protection circuit of figure 48 is widely identical to that of the transmitter
(figure 47). This is necessary because no current limiting resistor of the desired dimension
may be introduced in the SR1 path.
The RC combination on the line side centre tap of the transformer compensates the LCL drop
in the frequency range between 200 kHz and 300 kHz. This drop is a consequence of the
10 nF capacitor at SR1 (which cannot be omitted). The resistor in this RC combination limits
the current through the capacitor when overvoltages are applied. This normally allows using a
capacitor rated at 400 V.
The resonance frequency of the RC combination must be matched to suite specific
compensation requirements.
Semiconductor Group
87
INFINEON [ Infineon ]
