Functional Description
2.5.4.1 Receive Signal Oversampling
In order to additionally reduce the bit error rate in severe conditions, the ISAC-S performs
oversampling of the received signal and uses majority decision logic. (Note: this feature is
implemented in TE and LT-T modes only).
As illustrated in figure 50, each received bit is sampled 29 times at 7.68-MHz clock intervals
inside the estimated bit window. The samples obtained are compared against a threshold
VTR1 or VTR2 (see section: Adaptive Receiver Characteristics).
If at least 16 samples have an amplitude exceeding the selected threshold, a logical "0" is
considered to be detected, otherwise a logical "1" (no signal) is considered detected.
-
VSR2 VSR1
or
VTR1
VTR2
0 V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Derived 192-kHz Receive Bit Period
ITD02361
Figure 50
S/T Receive Signal Oversampling
Semiconductor Group
89
INFINEON [ Infineon ]
