Functional Description
2.5.4.3 Level Detection Power Down (TE mode)
In power down state, (see chapter 3.3.1) only an analog level detector is active. All clocks,
including the IOM interface, are stopped. The data lines are "high", whereas the clocks are
"low".
An activation initiated from the exchange side (Info 2 on S-bus detected) will have the
consequence that a clock signal is provided automatically.
From the terminal side an activation must be started by setting and resetting the SPU-bit in the
SPCR register (see chapter 4).
2.5.5
Timing Recovery
NT and LT-S
In NT and LT-S modes, the 192-kHz transmit bit clock is synchronized to the IOM clock. In the
receive direction two cases have to be distinguished depending on whether a bus or a point-
to-point operation is programmed in ADF1 (IOM-1) or SQXR (IOM-2) register (see figure 52):
– In a bus configuration (CFS=1), the 192-kHz receive bit clock is identical to the transmit bit
clock, shifted by 4.6 µs with respect to the transmit edge. According to CCITT I.430, the
receive frame shall be shifted by two bits with respect to the transmit frame.
– In a point-to-point or extended passive bus configuration (CFS=0), the 192-kHz receive bit
clock is recovered from the receive data stream on the S interface. The sampling instant for
the receive bits is shifted by 3.9 µs with respect to the leading edge of the derived receive
clock. According to CCITT I.430, the receive frame can be shifted by 2-8 bits with respect
to the transmit frame at the LT-S (NT). However, note that other shifts are also allowed by
the ISAC-S (including 0).
Semiconductor Group
91
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