Functional Description
Protection Circuit for Symmetrical Receivers
Figure 49 illustrates the external circuitry used in combination with a symmetrical receiver
(PEB 2086 ISAC-S) Protection of symmetrical receivers is rather comfortable.
1.8 kΩ
8.2 kΩ
SR2
SR1
47 pF
VDD
8.2 kΩ
S0 Bus
GND
1.8 kΩ
47 pF
ITS05643
Figure 49
External Circuitry for Symmetrical Receivers
Between each receive line and the transformer a 10 kΩ resistor is used. This value is split into
two resistors: one between transformer and protection diodes for current limiting during the
96 kHz test, and the second one between input pin and protection diodes to limit the maximum
input current ot the chip.
With symmetrical receivers no difficulties regarding LCL measurements are observed;
compensation networks thus are obsolete.
In order to comply to the physical requirements of CCITT recommendation I.430 and
considering the national requirements concerning overvoltage protection and electromagnetic
compability (EMC), the ISAC-S needs additional circuitry. Useful hints of how to design such
interface circuitry are also contained in the Application Note "S/T interface circuitry using the
PEB 2080 SBC or PEB 2085 ISAC-S".
2.5.4
Receiver Functions
Semiconductor Group
88
INFINEON [ Infineon ]
