Functional Description
ISAC R -S
2085
PEB
ISAC R -S
2085
PEB
<
1 k Ω
SR1
SR2
UF1
2.5 V
SX1
2.1 V
_
<
Ι
13.4 mA
+
SX2
_
2.1 V
ITS02358
ITS02357
IOM R -S
2086
PEB
ISAC R -S
2085
PEB
50 kΩ
SX1
SX2
2.1 V
40 kΩ
SR1
SR2
_
+
_
<
Ι
13.4 mA
40 kΩ
50 kΩ
2.1 V
2.5V
ITS05630
ITS02358
Figure 45
Equivalent Internal Circuits of Receiver and Transmitter Stages
The transmitter of the PEB 2086 ISAC-S is identical to that of both the PEB 2080 SBC and
PEB 2085 ISAC-S, hence, the line interface circuitry should be the same. The external
resistors (20 ... 40 Ω) are required in order to adjust the output voltage to the pulse mask
(nominal 750 mV according CCITT I.430, to be tested with the command "TM1") on the one
hand and in order to meet the output impedance of minimum 20 Ω (tansmission of a binary one
according to CCITT I.430, to be tested with the command "TM2") on the other hand.
The S-bus receiver of the PEB 2085 is designed as a threshold detector with adaptively
switched threshold levels. Pin SR1 delivers 2.5 V as an output, which is the virtual ground of
the input signal on pin SR2.
The S-bus receiver of the PEB 2086 has been changed to a symmetrical one. This results in
a simplification of the external circuitry and PCB layout to meet the I.430 receiver input
impedance specification.
Semiconductor Group
83
INFINEON [ Infineon ]
