PEB 2086
Description of the receive PLL (RPLL) of the ISAC-S
The receive PLL performs phase tracking each 250 µs after detecting the phase between the
F/L transition of the receive signal and the recovered clock. Phase adjustment is done by
adding or subtracting 130 ns to or form a 1.536-MHz clock cycle. The 1.536-MHz clock is than
used to generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz and 512-kHz
clocks to have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC output
in TE mode is set to a specific phase relationship, thus causing once an irregular FSC timing.
Reset
Table 34
Reset Signal Characteristics
Parameter
Symbol Limit Values
min.
Unit
Test Condition
Length of active
high state
t
RST
4
ms
Power on/Power Down
to Power Up (Standby)
2 × DCL
During Power Up (Standby)
clock cycles
t RST
RST
ITD02396
Figure 106
Semiconductor Group
266
INFINEON [ Infineon ]
