Electrical Characteristics
Table 33
X1 Clock Characteristics (LT-S mode)
Parameter
Symbol
Limit Values
typ.
Unit
Test Condition
min.
max.
(LT-S) 7680 kHz
t
t
t
PO
– 100 ppm 130.21 100 ppm ns
osc ± 100 ppm
osc ± 100 ppm
osc ± 100 ppm
WHO
WLO
65
65
ns
ns
Jitter
In TE mode, the timing extraction jitter of the ISAC-S conforms to CCITT Recommendation
I.430 (– 7% to + 7% of the S-interface bit period).
In the NT and LT-S applications, the clock input DCL is used as reference clock to provide the
192-kHz clock for the S-line interface. In the case of a plesiochronous 7.68-MHz clock
generated by an oscillator, the clock DCL should have a jitter less than 100 ns peak-to-peak.
(In the case of a zero input jitter on DCL the ISAC-S generates at most 130 ns "self-jitter" on
the S interface.)
In the case of a synchronous*) 7.68-MHz clock (input XTAL1), the ISAC-S transfers the input
jitter of XTAL1, DCL and FSC1 to the S interface. The maximum jitter of the NT/LT-S output is
limited to 260 ns peak-to-peak (CCITT I.430).
Description of the Transmit PLL (XPLL) of the ISAC®-S
Function of the XPLL
The XPLL generates a 1.536-MHz clock synchronized to the DCL 512-kHz clock by
modification of the counter’s divider ratio. The 1.536-MHz clock is then divided to 192 kHz and
512 kHz. The 512 kHz is used as the looped back clock and compared to the 512-kHz DCL in
the phase detector. A four bit up/down counter integrates the phase information to prevent
tracking steps in presence of high frequency input jitter (see figure 99).
Jitter considerations in case of a synchronous 7.68-MHz clock
After the XPLL has locked once, no more tracking steps are performed because there is a fixed
divider ratio of 15 between 7.68 MHz and DCL. Therefore the input jitter at DCL and 7.68 MHz
is transferred transparently to the S/T interface (192 kHz).
Jitter considerations in case of a plesiochronous 7.68-MHz clock (crystal)
Each tracking step of the XPLL produces an output jitter of 130 ns pp. In case of non-zero input
jitter at DCL, this input jitter is increased by 130 ns pp. However, if the input jitter frequency is
high enough (in the range of 25 kHz and higher) the four bit up/dn counter works as a loop filter
and thus the XPLL attenuates the input jitter to zero.
*)
fixed divider ratio between XTAL1 and DCL
Semiconductor Group
264
INFINEON [ Infineon ]
