Register Description
MRC1,0 MR Bit Control (IOM Channel 1,0)
Determines the value of the MR bit:
0: MR always "1". In addition, the MDR1/MDR0 interrupt is blocked, except for the
first byte of a packet (if MRE1/0 = 1).
1: MR internally controlled by the ISAC-S according to MONITOR channel
protocol. In addition, the MDR1/MDR0 interrupt is enabled for all received bytes
according to the MONITOR channel protocol (if MRE1 0 = 1).
MXE1,0 MONITOR Transmit Interrupt Enable (IOM channel 1,0)
MONITOR interrupt status MDA1/0, MAB1/0 generation is enabled (1) or
masked (0).
MXC1,0 MX Bit Control (IOM Channel 1,0)
Determines the value of the MX bit:
0: MX always "1".
1: MX internally controlled by the ISAC-S according to MONITOR channel
protocol.
4.3.19 S, Q Channel Receive Register
SQRR
Read
Address 3B
H
Value after reset: 0X
H
7
0
IDC
CFS
CI1E
SYN SQR1 SQR2 SQR3 SQR4
IDC
Read-Back of Programmed IDC Bit (see SQXR register)
Read-Back of Programmed CFS Bit (see SQXR register)
Read-Back of Programmed CI1E Bit (see SQXR register)
CFS
CI1E
SYN
Synchronization State
Used in TE/LT-T mode only (pin M1 = 0).
The S/T receiver has synchronized to the received F and M bits (1) or has not (0).
A
SQR1-4 Received S/Q Bits
TE/LT-T mode (pin M1 = 0): Received S bits in frames 1, 6, 11 and 16,
respectively.
LT-S/NT mode (pin M1 = 1): Received F bits in frames 1, 6, 11 and 16,
A
respectively.
Semiconductor Group
241
INFINEON [ Infineon ]
