Register Description
1: The IOM interface clock and frame signals are normally inactive
Power Down").
For activating the S-interface the "Power Up" state can be induced by software
(SPU-bit in SPCR register).
After that the S-interface can be activated with the C/I command Activate
Request (AR 8/10/L).
The "Power Down" state can be reached again with the C/I command
Deactivation Indication (DIU).
Note:
After reset the IOM interface is always active. To reach the "Power Down" state
the CFS-bit has to be set.
LT-S Mode:
0: In point-to-point configurations (S-bus) the bit and frame clock are recovered
from the received bit stream on the S-interface with the internal PLL.
This is to tolerate a variable bit shift of 2- to 8-bit times between the transmitted
and the received frame (max distance of 1.0 ... 1.5 km).
1: In bus configurations only a fixed bit shift of 2-bit times is accepted according to
CCITT (distances up to 150 m).
(Also refer to chapter 2.5.5)
LT-T Mode:
CFS has to be set to "0" always.
C/I channel 1 Interrupt Enable
Interrupt generation of CIR0:CIC1 is enabled (1) or masked (0).
CI1E
SQIE
S, Q Interrupt Enable
Generation of CIR0:SQC status (and the accompanying CISQ interrupt is enabled
(1) or masked (0).
SQX1-4 Transmitted S/Q Bits
TE/LT-T mode (pin M1 = 0): transmitted F bits in frames 1, 6, 11 and 16,
A
respectively.
LT-S/NT mode (pin M1 = 1): transmitted S bits in frames 1, 6, 11 and 16,
respectively.
Semiconductor Group
243
INFINEON [ Infineon ]
