Register Description
4.3.20 S, Q Channel Transmit Register
SQXR
Write
Address 3B
H
Value after reset: TE/LT-T mode (pin M1 = 0): 0F
H
LT-S/NT mode (pin M1 = 1): 00
H
7
0
IDC
CFS
CI1E
SQIE SQX1 SQX2 SQX3 SQX4
IDC
IOM Direction Control
Terminal mode (SPCR:SPM = 0):
0: Master (normal) mode
Layer 2 transmits IOM channel 0 and 2 on IDP1, channel 1 on IDP0.
1: Slave (test) mode
Layer 2 transmits IOM channel 0, 1 and 2 on IDP1.
Non-terminal mode (SPCR:SPM = 1):
0: normal mode
MONITOR, D- and C/I channels are transmitted on IDP1 from layer 2
to layer 1.
1: reversed (test) mode
MONITOR, D- and C/I channels are transmitted on IDP0 from layer 2
to the system.
Note: Also refer to chapter 2.4.2
CFS
Configuration Select
This bit determines clock relations and recovery on S/T and IOM interfaces.
TE Mode
0: The IOM interface clock and frame signals are always active, "Power Down" state
included.
The states "Power Down" and "Power Up" are thus functionally identical except
for the indication: PD = 1111 and PU = 0111.
With the C/I command Timing (TIM) the processor can enforce the "Power Up"
state.
With C/I command Deactivation Indication (DIU) the "Power Down" state is
reached again.
However, it is also possible to activate the S-Interface directly with the C/I
command Activate Request (AR 8/10/L) without the TIM command.
Semiconductor Group
242
INFINEON [ Infineon ]
