Register Description
Note: ST0/1 and SC0/1 are useful for synchronizing MP accesses and
receive/transmit operations.
4.3.14 B2 Channel Register
B2CR
Read
Address 38
H
7
0
Used only in terminal mode (SPCR:SPM = 0).
Contains the value received in the IOM channel B2, if programmed
(see C2C1, C2C0, SPCR register).
4.3.15 Additional Feature Register 1
ADF1
Write
Address 38
H
Value after reset: 00
H
7
0
WTC1 WTC2 TEM
PFS
IOF/
0/
0/
ITF
CSEL2 CSEL1 CSEL0
WTC1, 2 Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (STCR:TSF = CIX0:RSS = 1) the
watchdog timer is started.
During every time period of 128 ms the processor has to program the WTC1- and
WTC2-bit in the following sequence:
WTC1
WTC2
1.
2.
1
0
0
1
to reset and restart the watchdog timer.
If not, the timer expires and a WOV interrupt (EXIR) together with a reset pulse is ge-
nerated.
TEM
PFS
Test Mode
In test mode (TEM = 1, PFS = 0) all layer-1 functions are disabled and the ISAC®-S
behaves like an ICC (PEB 2070) device.
Prefilter Select
Semiconductor Group
237
INFINEON [ Infineon ]
