Register Description
4.1.11 Receive Frame Byte Count Low
RBCL
Read
Address 25
H
Value after reset: 00
H
7
0
RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0
RBC7-0 Receive Byte Count
Eight least significant bits of the total number of bytes in a received message. Bits
RBC4-0 indicate the length of the data block currently available in the RFIFO, the
other bits (together with RBCH) indicate the number of whole 32-byte blocks
received.
If exactly 32 bytes are received RBCL holds the value 20 .
H
4.1.12 Transmit Address 2
XAD2
Write
Address 25
H
7
0
Used in auto-mode only.
XAD2 contains the second programmable address byte, whose function depends on
the selected address mode:
* 2-Byte Address Field
XAD2 is the low byte (TEI in the ISDN) of the 2-byte address field.
* 1-Byte Address Field
According to the X.25 LAPB protocol, XAD2 is the address of a response frame.
Note: See note to XAD1 register description.
4.1.13 Received SAPI Register
SAPR
Read
Address 26
H
7
0
When transparent mode 1 is selected, SAPR contains the value of the first address
byte of a receive frame.
Semiconductor Group
211
INFINEON [ Infineon ]
