CoolSET®-F3R
ICE3BR4765J
Functional Description
3.3.1
PWM-OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
RSense connected to pin CS. RSense converts the source
current into a sense voltage. The sense voltage is
amplified with a gain of 3.3 by PWM OP. The output of
the PWM-OP is connected to the voltage source V1.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
Figure 6).
Soft-Start Comparator
PWM Comparator
FB
C8
PWM-Latch
Oscillator
VOSC
time delay
circuit (156ns)
3.3.2
PWM-Comparator
Gate Driver
X3.3
The PWM-Comparator compares the sensed current
signal of the integrated CoolMOS® with the feedback
signal VFB (see Figure 8). VFB is created by an external
optocoupler or external transistor in combination with
the internal pull-up resistor RFB and provides the load
information of the feedback circuitry. When the
amplified current signal of the integrated CoolMOS®
exceeds the signal VFB the PWM-Comparator switches
off the Gate Driver.
0.67V
10kΩ
R1
T2
V1
PWM OP
C1
Voltage Ramp
5V
Figure 6
Improved Current Mode
Soft-Start Comparator
RFB
FB
VOSC
PWM-Latch
C8
max.
Duty Cycle
PWM Comparator
0.67V
t
Voltage Ramp
Optocoupler
PWM OP
CS
0.67V
FB
X3.3
Improved
Current Mode
t
Gate Driver
156ns time delay
Figure 8
PWM Controlling
t
Figure 7
Light Load Conditions
Version 2.5
10
19 Nov 2012
INFINEON [ Infineon ]
