CoolSET®-F3R
ICE3BR4765J
Functional Description
The Undervoltage Lockout monitors the external Current Mode means the duty cycle is controlled by the
supply voltage VVCC. When the SMPS is plugged to the slope of the primary current. This is done by comparing
main line the internal Startup Cell is biased and starts the FB signal with the amplified current sense signal.
to charge the external capacitor CVCC which is
connected to the VCC pin. This VCC charge current is
controlled to 0.9mA by the Startup Cell. When the VVCC
exceeds the on-threshold VCCon=18V the bias circuit
are switched on. Then the Startup Cell is switched off
by the Undervoltage Lockout and therefore no power
losses present due to the connection of the Startup Cell
to the Drain voltage. To avoid uncontrolled ringing at
switch-on, a hysteresis start up voltage is implemented.
The switch-off of the controller can only take place
when VVCC falls below 10.5V after normal operation
was entered. The maximum current consumption
before the controller is activated is about 150μA.
Amplified Current Signal
FB
0.67V
Driver
t
t
When VVCC falls below the off-threshold VCCoff=10.5V,
the bias circuit is switched off and the soft start counter
is reset. Thus it is ensured that at every startup cycle
the soft start starts at zero.
ton
The internal bias circuit is switched off if Auto Restart
Mode is entered. The current consumption is then
reduced to 150μA.
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart
Mode does not require re-cycling the AC line.
Figure 5
Pulse Width Modulation
In case the amplified current sense signal exceeds the
FB signal the on-time Ton of the driver is finished by
resetting the PWM-Latch (see Figure 5).
When Active Burst Mode is entered, the internal Bias is
switched off most of the time but the Voltage Reference
is kept alive in order to reduce the current consumption
below 450μA.
The primary current is sensed by the external series
resistor RSense inserted in the source of the integrated
CoolMOS®. By means of Current Mode regulation, the
secondary output voltage is insensitive to the line
variations. The current waveform slope will change with
the line variation, which controls the duty cycle.
The external RSense allows an individual adjustment of
the maximum source current of the integrated
CoolMOS®.
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
by VOSC. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
3.3
Improved Current Mode
Soft-Start Comparator
PWM-Latch
FB
R
Q
C8
Driver
S
Q
0.67V
PWM OP
x3.3
Voltage Ramp is
a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
the inverted VOSC signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing VFB below that
threshold.
CS
Improved
Current Mode
Figure 4
Current Mode
Version 2.5
9
19 Nov 2012
INFINEON [ Infineon ]
