AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
AA
3
ro
Autoneg Ability
0B
1B
, PHY cannot auto-negotiate
, PHY can auto-negotiate
LS
JD
EC
2
1
0
ro, ll
ro, lh
ro
Link Status
Note:lh: Latch Low
0B
1B
, link is down
, link is up
Jabber Detect
Only used in 10Base-T mode. Reads as 0 in 100Base-TX mode.
Note:lh: Latch High
1B
, jabber condition detected
Extended Capability
0B
1B
, basic register set capabilities only
, extended register capabilities
Register 2 and 3
Each PHY has an unique identifier, which is assigned to the device.
The identifier contains a total of 32 bits, which consists of the following: 22 bits of a 24bit organizationally unique
identifier (OUI) for the manufacturer; a 6-bit manufacturer’s model number; a 4-bit manufacturer’s revision number.
For an explanation of how the OUI maps to the register, please refer to IEEE 802-1990 clause 5.1.
There is physically only one of each of these registers for all six network(MDI) ports. When reading this register
the port number is ignored.
Data Sheet
86
Rev. 1.51, 2005-11-30
INFINEON [ Infineon ]
