IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
72-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
ChipSelectpin(RCS)areprovidedontheFIFO.TheSynchronousReadChip
SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedanceorLOWimpedance.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
BoundaryScanArchitecture.
TheTeraSyncFIFOhas thecapabilityofoperatingits ports (writeand/or
read)ineitherLVTTLorHSTLmode,eachportsselectionindependentofthe
other.ThewriteportselectionismadeviaWHSTLandthereadportselection
via RHSTL. AnadditionalinputSHSTLis alsoprovided, this allows the user
toselectHSTLoperationforotherpinsonthedevice(notassociatedwiththe
write or read ports).
DESCRIPTION (CONTINUED)
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas
shown in Table 1.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread
outoftheFIFOinsmallword(x18/x9)format.IfBig-Endianmodeisselected,
thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill
bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See
Figure 5 for Bus-Matching Byte Arrangement.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26and
D35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed
Paritymodeisselected,thenD8andD17areassumedtobevalidbits. IPmode
is selectedduring MasterResetbythestateoftheIPinputpin.
The IDT72T7285/72T7295/72T72105/72T72115 are fabricated using
IDT’shighspeedsubmicronCMOStechnology.
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
