ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Absolute Max
Symbol
VDDA
VDD
Parameter
Min
Max
Units
3.3V Core Supply Voltage
3.3V Output Supply Voltage
VDD + 0.5V
VDD + 0.5V
V
GND - 0.5
-65
V
Ts
Storage Temperature
Case Temperature
Input ESD protection
human body model
150
115
°C
°C
Tcase
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = Tambient; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Tambcom
Tambind
Commercial range
Industrial range
0
70
85
°C
°C
1
1
Tambient
-40
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
1
Input Low Voltage
Input High Current
VIL
IIH
3.3 V +/-5%
VIN = VDD
VSS - 0.3
-5
0.8
5
V
1
1
uA
VIN = 0 V; Inputs with no pull-
up resistors
IIL1
IIL2
-5
uA
uA
1
1
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
-200
75
27
Full Active, CL = Full load;
all differential pairs tri-stated
VDD = 3.3 V
100
50
105
7
mA
mA
MHz
nH
1
1
1
1
1
1
Operating Supply Current
IDD3.3OP
Input Frequency3
Pin Inductance1
Fi
80
100
Lpin
CIN
Logic Inputs
5
pF
Input Capacitance1
Clk Stabilization1,2
COUT
Output pin capacitance
4.5
pF
From VDD Power-Up to 1st
clock
TSTAB
1.8
33
45
ms
kHz
KHz
1
1
1
Modulation Frequency
Spread Spectrum Modulation
Frequency
Triangular Modulation
30
25
fMOD
Lexmark Modulation
PLL Bandwidth when
PLL_BW=0
400
1.2
KHz
MHz
1
1
PLL Bandwidth
BW
VDD
PLL Bandwidth when
PLL_BW=1
SMBus Voltage
2.7
4
5.5
0.4
V
V
1
1
1
Low-level Output Voltage
VOLSMBUS @ IPULLUP
IPULLUP SMBus SDATA pin
Current sinking at VOL = 0.4 V
SCLK/SDATA
mA
TRI2C
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
300
ns
ns
1
1
Clock/Data Rise Time
SCLK/SDATA
TFI2C
(Min VIH + 0.15) to (Max VIL - 0.15)
Clock/Data Fall Time
1Guaranteed by design and characterization, not 100% tested in production.
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
852 REV K 04/01/10
3
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
