ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Pin Configuration
Power Groups
Pin Number
PLL_BW 1
CLK_INT 2
CLK_INC 3
20 VDDA
19 GNDA
Description
VDD
GND
5,9,12,16
9
6,15
6
PCI Express Outputs
SMBUS
IREF
18 IREF
17 **CLKREQ1#
4
5
**CLKREQ0#
VDD
20
20
19
19
Analog VDD & GND for PLL core
16
15 GND
VDD
GND 6
7
14
13
PCIEXT0
PCIEXC0
VDD
PCIEXT1
PCIEXC1
8
9
10
12 VDD
11 SMBCLK
SMBDAT
Note: Pins preceeded by '**' have internal
120K ohm pull down resistors
20-pin SSOP & TSSOP
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = low, 1= high
1
PLL_BW
INPUT
2
3
CLK_INT
CLK_INC
INPUT
INPUT
"True" reference clock input.
"Complementary" reference clock input.
Output enable for SRC/PCI Express output pair '0'
0 = enabled, 1 = tri-stated
4
**CLKREQ0#
INPUT
5
VDD
POWER
POWER
OUTPUT
OUTPUT
POWER
I/O
Power supply, nominal 3.3V
6
GND
Ground pin.
7
PCIEXT0
PCIEXC0
VDD
True clock of differential PCI_Express pair.
8
Complement clock of differential PCI_Express pair.
Power supply, nominal 3.3V
9
10
11
12
13
14
15
16
SMBDAT
SMBCLK
VDD
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
INPUT
POWER
OUTPUT
OUTPUT
POWER
POWER
PCIEXC1
PCIEXT1
GND
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Ground pin.
VDD
Power supply, nominal 3.3V
Output enable for SRC/PCI Express output pair '1'
0 = enabled, 1 = tri-stated
17
**CLKREQ1#
IREF
INPUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
18
OUTPUT
19
20
GNDA
VDDA
POWER
POWER
Ground pin for the PLL core.
3.3V power for the PLL core.
Note:
Pins preceeded by '**' have internal 120K ohm pull down resistors
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
852 REV K 04/01/10
2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
