ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
General SMBus serial interface information for the ICS9DB102
How to Write:
• Controller (host) sends a start bit.
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D4(h)
• ICS clock will acknowledge
• Controller (host) sends the write address D4(h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D5(h)
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• Controller (host) sends a Stop bit
• ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
Index Block Write Operation
ICS (Slave/Receiver)
ICS (Slave/Receiver)
Controller (Host)
starT bit
T
starT bit
T
Slave Address D4(h)
Slave Address D4(h)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D5(h)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
852 REV K 04/01/10
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
