DATASHEET
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Description
Features/Benefits
The ICS9DB102 zero-delay buffer supports PCI Express
clocking requirements. The ICS9DB102 is driven by a differential
SRC output pair from an ICS CK410/CK505-compliant main
clock. It attenuates jitter on the input clock and has a selectable
PLL Band Width to maximize performance in systems with or
without Spread-Spectrum clocking.
•
CLKREQ# pin for outputs 1 and 4/output enable for Express
Card applications
•
•
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
•
Spread Spectrum Compatible/tracks spreading input clock
for low EMI
•
•
SMBus Interface/unused outputs can be disabled
Industrial temperature range available
Output Features
2 - 0.7V current mode differential output pairs (HCSL)
•
Key Specifications
Cycle-to-cycle jitter < 35ps
•
•
Output-to-output skew < 25ps
Functional Block Diagram
CLKREQ0#
CLKREQ1#
PCIEX0
PCIEX1
CLK_INT
SPREAD
COMPATIBLE
PLL
CLK_INC
PLL_BW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
852 REV K 04/01/10
1
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
