ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Reset: Hardware Reset and Power-Down
The table below lists the significant time periods for the hardware reset and power-down reset. The time periods
consist of timings of signals on the following pins:
• REF_IN
• RESETn
• TXCLK
The Hardware Reset and Power-Down Timing Diagram shows the timing diagram for the time periods.
Time
Period
Parameter
Conditions Min. Typ. Max Units
.
t1
t2
t3
RESETn Active to Device Isolation and Initialization
Minimum RESETn Pulse Width
–
–
–
–
200
–
60
–
–
ns
ns
RESETn Released to TXCLK Valid
35
500
ms
Hardware Reset and Power-Down Timing Diagram
REF_IN
RESETn
t1
t2
t3
TXCLK Valid
Power
Consumption
(AC only)
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
46
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
