ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
The table below lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
The 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for
the time periods.
Time
Parameter
Conditions Min. Typ. Max. Units
Period
t1
t2
TXEN Asserted to CRS Assert
0
0
–
2
2
4
Bit times
Bit times
TXEN De-Asserted to CRS De-Asserted
10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
t2
TXEN
TXCLK
CRS
t1
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
42
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
