ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Reset: Power-On Reset
The table below lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
• VDD
• TXCLK
The Power-On Reset Timing Diagram shows the timing diagram for the time periods.
Time
Parameter
Conditions Min. Typ. Max. Units
Period
t1
VDD ≥ 2.7 V to Reset Complete
–
40
45
500
ms
Power-On Reset Timing Diagram
2.7 V
VDD
t1
TXCLK
Valid
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
45
ICS1894-40
REV G 060110