ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
The table below lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time
periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• CRS
• COL
The 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram shows the timing diagram for the time
periods.
Time
Parameter
Conditions
Min. Typ. Max. Units
Period
t1
t2
First Bit of /J/ into TP_RX to CRS Assert †
–
10
9
–
–
14
13
Bit times
Bit times
First Bit of /J/ into TP_RX while
Half-Duplex Mode
Transmitting Data to COL Assert †
t3
t4
First Bit of /T/ into TP_RX to CRS
De-Assert ‡
–
13
–
–
18
18
Bit times
Bit times
First Bit of /T/ Received into TP_RX to
COL De-Assert ‡
Half-Duplex Mode 13
†The IEEE maximum is 20 bit times.
‡The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram
First bit
First bit of /T/
†
TP_RX
t3
t1
CRS
COL
t4
t2
†
Shown
unscrambled.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
44
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
