ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.10 100M / MII Media Independent Interface: Transmit Latency
Table 10-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time
periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• TXD (that is, TXD[3:0])
• TP_TX (that is, TP_TXP and TP_TXN)
Figure 10-11 shows the timing diagram for the time periods.
Table 10-17. MII / 100M Stream Interface Transmit Latency
Time
Period
Parameter
Conditions
Min. Typ. Max.
2.8
Units
t1
TXEN Sampled to MDI Output of First MII mode
Bit of /J/ †
–
3
Bit times
† The IEEE maximum is 18 bit times.
Figure 10-11. MII / 100M Stream Interface Transmit Latency Timing Diagram
TXEN
TXCLK
TXD
Preamble /J/
Preamble /K/
TP_TX†
t1
† Shown
unscrambled.
ICS1893AF, Rev. D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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