ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.8 10M Media Independent Interface: Receive Latency
Table 10-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of
signals on the following pins:
• TP_RX (that is, the MII TP_RXP and TP_RXN pins)
• RXCLK
• RXD
Figure 10-9 shows the timing diagram for the time periods.
Table 10-15. 10M MII Receive Latency
Time
Period
Parameter
Conditions Min. Typ. Max.
10M MII 6.5
Units
t1
First Bit of /5/ on TP_RX to /5/D/ on RXD
–
7
Bit times
Figure 10-9. 10M MII Receive Latency Timing Diagram
TP_RX†
RXCLK
RXD
5
5
5
D
t1
† Manchester
encoding is
not shown.
ICS1893AF, Rev. D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
121
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