ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.9 10M Media Independent Interface: Transmit Latency
Table 10-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of
timings of signals on the following pins:
• TXEN
• TXCLK
• TXD (that is, TXD[3:0])
• TP_TX (that is, TP_TXP and TP_TXN)
Figure 10-10 shows the timing diagram for the time periods.
Table 10-16. 10M MII Transmit Latency Timing
Time
Period
Parameter
Conditions Min. Typ. Max.
10M MII 1.2
Units
t1
TXD Sampled to MDI Output of First Bit
–
2
Bit times
Figure 10-10. 10M MII Transmit Latency Timing Diagram
TXEN
TXCLK
TXD
5
5
5
TP_TX†
t1
† Manchester
encoding is
not shown.
ICS1893AF, Rev D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
122
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
