ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
Table 10-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The
time periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• CRS
• COL
Figure 10-15 shows the timing diagram for the time periods.
Table 10-21. 100M MDI Input-to-Carrier Assertion/De-Assertion Timing
Time
Parameter
Conditions
Min. Typ. Max.
Units
Period
t1
t2
First Bit of /J/ into TP_RX to CRS Assert †
–
10
9
–
–
14 Bit times
13 Bit times
First Bit of /J/ into TP_RX while
Half-Duplex Mode
Transmitting Data to COL Assert †
t3
t4
First Bit of /T/ into TP_RX to CRS
De-Assert ‡
–
13
–
–
18 Bit times
18 Bit times
First Bit of /T/ Received into TP_RX to
COL De-Assert ‡
Half-Duplex Mode 13
† The IEEE maximum is 20 bit times.
‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 10-15. 100M MDI Input to Carrier Assertion / De-Assertion Timing Diagram
First bit
First bit of /T/
TP_RX†
t3
t1
CRS
COL
t4
t2
† Shown
unscrambled.
ICS1893AF, Rev. D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
127
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