ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.13 100M MII Media Independent Interface: Receive Latency
Table 10-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The
time periods consist of timings of signals on the following pins:
• TP_RX (that is, TP_RXP and TP_RXN)
• RXCLK
• RXD (that is, RXD[3:0])
Figure 10-14 shows the timing diagram for the time periods.
Table 10-20. 100M MII / 100M Stream Interface Receive Latency Timing
Time
Period
Parameter
Conditions
Min. Typ. Max.
16 17
Units
t1
First Bit of /J/ into TP_RX to /J/ on RXD 100M MII
–
Bit times
Figure 10-14. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram
TP_RX†
RXCLK
RXD
t1
† Shown
unscrambled.
ICS1893AF, Rev D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
126
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