ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5.4 100M MII: Synchronous Transmit Timing
Table 10-11 lists the significant time periods for the 100M MII Interface synchronous transmit timing. The
time periods consist of timings of signals on the following pins:
• TXCLK
• TXD[3:0]
• TXEN
• TXER
Figure 10-5 shows the timing diagram for the time periods.
Table 10-11. 100M MII / 100M Stream Interface: Synchronous Transmit Timing
Time
Parameter
Conditions
Min.
Typ. Max. Units
Period
t1
t2
TXD[3:0], TXEN, TXER Setup to TXCLK Rise
TXD[3:0], TXEN, TXER Hold after TXCLK Rise
–
–
15
0
–
–
–
–
ns
ns
Figure 10-5. 100M MII / 100M Stream Interface Synchronous Transmit Timing Diagram
TXCLK
TXD[3:0]
TXEN
TXER
t1
t2
ICS1893AF, Rev. D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
117
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
